Due to their increased integration density and functionality, the design of electronic integrated circuits has become ever more complex.
The complexity of the electronic integrated circuits requires particular strategies in the design cycle. Conventional strategies are “top down”, “bottom up”, or similarly structured approaches.
In a top down approach for instance, the design of a particular integrated circuit starts at a relatively high level of abstraction, and thereafter the relevant design is progressively refined at increasingly lower levels of abstraction, by starting at a “systems level”, proceeding via an “algorithm register transfer and/or logic level” to a “circuit level” etc., until finally the mask data required for manufacturing the components is obtained.
A register transfer level (RTL) description is a description of an electronic circuit determining the data flow between registers, which store information between clock cycles in an electronic circuit. An RTL description determines where this information is stored, what it represents, and how it is passed through the circuit during its operation. Thus, an RTL description determines how data is transformed as it is passed from register to register.
On a logical level, the logical circuits are designed using simulation systems or synthesis tools wherein a circuit design is expressed in a proprietary language or hardware description language (HDL) such as RTL (register transfer level). An example for a hardware description language is Verilog as described by IEEE Standard 1364.1, “Standard for Verilog Register Transfer Level Synthesis” and an example for a simulation system or synthesis tools is NCVerilog available from Cadence, 2655 Scely Avenue, San José, Calif. 95134.
By using a hardware description language such as RTL a synthesis tool may be used to express a particular electronic circuit design. Once expressed in RTL the electronic circuit design may be altered and/or refined in order to optimize it according to predetermined design criteria.
The place value of a binary digit (bit) in a binary number expresses the binary power represented by the bit to constitute the binary number.
While serial arithmetical or logical operations are carried out in consecutive steps according to a given design of an electronic circuit, and controlled by the clock cycles generated in the electronic circuit, parallel arithmetic or logical operations are executed concurrently with one clock cycle.
Relying on synthesis tools to optimize an electronic circuit design is cumbersome, time consuming and may be error prone.
Therefore, it is an object of the present invention to provide a method and system to optimize the design of electronic circuit designs to comprising parallel arithmetic operations.